View CS43L21-DNZR_1782407.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

copyright ? cirrus logic, inc. 2006 (all rights reserved) http://www.cirrus.com advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. july '06 ds723a1 low power, stereo digital to analog converter features ? 98 db dynamic range (a-wtd) ? -86 db thd+n ? headphone amplifier - gnd centered ? on-chip charge pump provides -va_hp ? no dc-blocking capacitor required ? 46 mw power into stereo 16 ? @ 1.8 v ? 88 mw power into stereo 16 ? @ 2.5 v ? -75 db thd+n ? digital signal processing engine ? bass & treble tone control, de-emphasis ? pcm mix w/independent vol control ? master digital volume control and limiter ? soft ramp & zero cross transitions ? beep generator ? tone selections across two octaves ? separate volume control ? programmable on & off time intervals ? continuous, periodic or one-shot beep selections ? programmable peak-d etect and limiter ? pop and click suppression system features ? 24-bit conversion ? 4 khz to 96 khz sample rate ? multi-bit delta sigma architecture ? low power operation ? stereo playback: 12.93 mw @ 1.8 v ? variable power supplies ? 1.8 v to 2.5 v digital & analog ? 1.8 v to 3.3 v interface logic ? power down management ? software mode (i2c ? & spi ? control) ? hardware mode (stand-alone control) ? digital routing/mixes: ? mono mixes ? flexible clocking options ? master or slave operation ? high-impedance digital output option (for easy muxing between dac and other data sources) ? quarter-speed mode - (i.e. allows 8 khz fs while maintaining a flat noise floor up to 16 khz) 1.8 v to 3.3 v multibit ? modulator charge pump left hp out right hp out serial audio input 1.8 v to 2.5 v pcm serial interface register configuration level translator reset hardware mode or i 2 c & spi software mode control data beep generator mux mux headphone amp - gnd centered headphone amp - gnd centered 1.8 v to 2.5 v switched capacitor dac and filter switched capacitor dac and filter digital signal processing engine cs43l21
2 ds723a1 cs43l21 applications ? portable audio players ? md players ? pdas ? personal media players ? portable game consoles ? smart phones ? wireless headsets general description the cs43l21 is a highly integrated, 24-bit, 96 khz, low power stereo dac. based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment be- tween 4 khz and 96 khz. the dac offers many features suitable for low po wer, portable syst em applications. the dac output path includes a digital signal process- ing engine. tone control provides bass and treble adjustment of four selectable corner frequencies. the mixer allows independent vo lume control for pcm mix, as well as a master digital volume control for the analog output. all volume level changes may be configured to occur on soft ramp and zero cross transitions. the dac also includes de-emphasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves. the stereo headphone amplifier is powered from a sep- arate positive supply and the integrated charge pump provides a negative supply. this allows a ground-cen- tered analog output with a wide signal swing and eliminates external dc-blocking capacitors. in addition to its many features, the cs43l21 operates from a low-voltage analog and digital core, making this dac ideal for portable systems that require extremely low power consumption in a minimal amount of space. the cs43l21 is available in a 32-pin qfn package in both commercial (-10 to +70 c) and automotive grades (-40 to +85 c). the cs43l21 customer dem- onstration board is also available for device evaluation and implementation suggestions. please see ?ordering information? on page 63 for complete details.
ds723a1 3 cs43l21 table of contents 1. pin descriptions - software (hardware) mode .................................................................. 6 1.1 digital i/o pin characteristics ........................................................................................... ................ 8 2. typical connection diagrams ................................................................................................ ... 9 3. characteristic and specificat ion tables ......... ................ ............. ............. ............. ......... 11 specified operating conditions ............................................................................................. 11 absolute maximum ratings ...................................................................................................... .11 analog output characteristics (commercial - cnz) ...................................................... 12 analog output characteristics (automotive - dnz) ...................................................... 13 line output voltage characteristics ................................................................................. 14 headphone output power characteristics ...................................................................... 15 combined dac interpolation & on-chip anal og filter response .. ................ ............ 16 switching specifications - serial port ............ ................ ................ ............. ............. ......... 16 switching specifications - i2c? control port ..... ................ ................. ................ ............ 18 switching characteristics - spi? control po rt ............................................................ 19 dc electrical characteristics .............................................................................................. 20 digital interface specifications & characteri stics ............ ................ ................ ......... 20 power consumption ............................................................................................................. ....... 21 4. applications ............................................................................................................... .................... 22 4.1 overview .................................................................................................................. ....................... 22 4.1.1 architecture ............................................................................................................ ............... 22 4.1.2 line & headphone outputs ................................................................................................ ... 22 4.1.3 signal processing engine ................................................................................................ ..... 22 4.1.4 beep generator ........... ............................................................................................... ........... 22 4.1.5 device control (hardware or software mode ) ...................................................................... 22 4.1.6 power management ........................................................................................................ ...... 22 4.2 hardware mode .............. ............................................................................................... ................. 23 4.3 analog outputs ............................................................................................................ ................... 24 4.3.1 de-emphasis filter ...................................................................................................... .......... 24 4.3.2 volume controls ......................................................................................................... ........... 25 4.3.3 mono channel mixer ...................................................................................................... ....... 25 4.3.4 beep generator ........... ............................................................................................... ........... 25 4.3.5 tone control ............................................................................................................ .............. 26 4.3.6 limiter ................................................................................................................. ................... 26 4.3.7 line-level outputs and filtering ........................................................................................ ... 27 4.3.8 on-chip charge pump ..................................................................................................... ..... 28 4.4 serial port clocking ...................................................................................................... .................. 28 4.4.1 slave ................................................................................................................... .................. 29 4.4.2 master .................................................................................................................. ................. 29 4.4.3 high-impedance digital output ........................................................................................... .. 30 4.4.4 quarter- and half-speed mode ............................................................................................ .30 4.5 digital interface formats ... .............................................................................................. ............... 30 4.6 initialization ............................................................................................................ ......................... 31 4.7 recommended power-up sequence ............................................................................................. 31 4.8 recommended power-down sequence ........................................................................................ 32 4.9 software mode ............................................................................................................. .................. 33 4.9.1 spi control ............................................................................................................. ............... 33 4.9.2 i2c control ............................................................................................................. ................ 33 4.9.3 memory address pointer (m ap) ............................................................................................ 35 4.9.3.1 map increment (i ncr) ............................................................................................... 35 5. register quick reference ................................................................................................... ..... 36 6. register description ....................................................................................................... ........... 39 6.1 chip i.d. and revision register (address 01h) (read only) ......................................................... 39
4 ds723a1 cs43l21 6.2 power control 1 (address 02h) ................... .......................................................................... ......... 39 6.3 speed control (address 03h) ............................................................................................... .......... 40 6.4 interface control (address 04h) ........................................................................................... .......... 41 6.5 dac output control (address 08h) .......................................................................................... ...... 41 6.6 dac control (address 09h) ................................................................................................. ........... 42 6.7 pcmx mixer volume control: pcma (address 10h) & pcmb (address 11h) ..................................................................................... 44 6.8 beep frequency & timing conf iguration (address 12h) ................................................................ 45 6.9 beep off time & volume (address 13h) ........ .............................................................................. .. 46 6.10 beep configuration & tone configuration (address 14h) ......... ................................................... 47 6.11 tone control (address 15 h) ............................................................................................... .......... 48 6.12 aoutx volume control: aouta (address 16h) & aoutb (address 17h) ....... .......................................................................... 49 6.13 pcm channel mixer (address 18h) .......................................................................................... .... 49 6.14 limiter threshold szc disable (address 19h) ............................................................................. 5 0 6.15 limiter release rate register (address 1ah) .............................................................................. 51 6.16 limiter attack rate register (address 1bh) ............................................................................... .. 52 6.17 status (address 20h) (read only) ......................................................................................... ...... 52 6.18 charge pump frequency (address 21h) ...................................................................................... 53 7. analog performance plots ................................................................................................... .54 7.1 headphone thd+n versus output power plots ............................................................................ 54 7.2 headphone amplifier efficiency ............................................................................................ .......... 56 8. example system clock frequenc ies .......... ................. ................ ................ ................ ......... 57 8.1 auto detect enabled ....................................................................................................... ................ 57 8.2 auto detect disabled ...................................................................................................... ................ 58 9. pcb layout considerations .................................................................................................. ... 59 9.1 power supply, grounding ................................................................................................... ............ 59 9.2 qfn thermal pad ........................................................................................................... ............... 59 10. digital filters ........................................................................................................... ................... 60 11. parameter definitions ..................................................................................................... ......... 61 12. package dimensions ....................................................................................................... .......... 62 thermal characteristics ....................................................................................................... .62 13. ordering information ..................................................................................................... ........ 63 14. references ................................................................................................................ .................... 63 15. revision history ......................................................................................................... ................ 63
ds723a1 5 cs43l21 list of figures figure 1.typical con nection diagram (software mode) .............. ............................................................. .. 9 figure 2.typical con nection diagram (hardware mode) ................. ......................................................... 1 0 figure 3.headphone output test load ........................................................................................... .......... 15 figure 4.serial a udio interface slave mode timing ............................................................................. ..... 17 figure 5.serial a udio interface master mode timing ............................................................................ .... 17 figure 6.control port timing - i2c ............................................................................................ ................. 18 figure 7.control port timing - spi format ..................................................................................... ........... 19 figure 8.output architecture .................................................................................................. ................... 24 figure 9.de-emphasis curve .................................................................................................... ................ 25 figure 10.beep configuration options .......................................................................................... ............ 26 figure 11.peak detect & limiter ............................................................................................... ................ 27 figure 12.master mode timing .................................................................................................. ............... 29 figure 13.tri-state sclk/lrck ................................................................................................. .............. 30 figure 14.i2s format .......................................................................................................... ....................... 30 figure 15.left-justified format ............................................................................................... .................. 31 figure 16.right-justified format (dac only) ................................................................................... ......... 31 figure 17.initialization flow chart ........................................................................................... .................. 32 figure 18.control port timing in spi mode ..................................................................................... ......... 33 figure 19.control port timing, i2c write ...................................................................................... ............. 34 figure 20.control port timing, i2c read ....................................................................................... ............ 34 figure 21.thd+n vs. output power per channel at 1.8 v (16 ? load) .................................................... 54 figure 22.thd+n vs. output power per channel at 2.5 v (16 ? load) .................................................... 54 figure 23.thd+n vs. output power per channel at 1.8 v (32 ? load) .................................................... 55 figure 24.thd+n vs. output power per channel at 2.5 v (32 ? load) .................................................... 55 figure 25.power dissipation vs. output power into stereo 16 ? ......................................................................56 figure 26.power dissipation vs. output power into stereo 16 ? (log detail) .......................................... 56 figure 27.passband ripple ..................................................................................................... .................. 60 figure 28.stopband ............................................................................................................ ....................... 60 figure 29.transition band ..................................................................................................... .................... 60 figure 30.transition band (detail) ............................................................................................ ................ 60 list of tables table 1. i/o power rails ...................................................................................................... ....................... 8 table 2. hardware mode feature summary ........................................................................................ ..... 23 table 3. mclk/lrck ratios ..................................................................................................... ............... 29
6 ds723a1 cs43l21 1. pin descriptions - so ftware (hardware) mode pin name # pin description lrck 1 left right clock ( input/output ) - determines which channel, left or right, is currently active on the serial audio data line. sda/cdin (mclkdiv2) 2 serial control data ( input / output ) - sda is a data i/o in i2c mode. cdin is the input data line for the control port interface in spi mode. mclk divide by 2 ( input ) - hardware mode: divides the mclk by 2 prior to all internal circuitry. scl/cclk (i2s/lj ) 3 serial control port clock ( input ) - serial clock for the serial control port. interface format selection ( input ) - hardware mode: selects between i2s & left-justified interface for- mats for the dac. ad0/cs (dem) 4 address bit 0 (i2c) / contro l port chip select (spi) ( input ) - ad0 is a chip address pin in i2c mode; cs is the chip-select si gnal for spi format. de-emphasis (input) - hardware mode: enables/disa bles the de-emphasis filter. va_hp 5 analog power for headphone (input) - positive power for the internal analog headphone section. flyp 6 charge pump cap positive node (input) - positive node for the extern al charge pump capacitor. gnd_hp 7 analog ground ( input ) - ground reference for the internal headphone/charge pump section. flyn 8 charge pump cap negative node (input) - negative node for the external charge pump capacitor. vss_hp 9 negative voltage from charge pump (output) - negative voltage rail for the internal analog head- phone section. 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 cs43l21 vd dgnd tsto(m/s ) mclk sdin sclk vss_hp aoutb aouta va agnd filt+ nic vq sda/cdin (mclkdiv2) scl/cclk (i2s/lj ) ado/cs (dem) flyp vl reset gnd_hp flyn tsto tsto tsto tsto tsto tsto tsto tsto va_hp lrck
ds723a1 7 cs43l21 aoutb aouta 10 11 analog audio output ( output ) - the full-scale output level is specified in the dac analog characteris- tics specification table va 12 analog power ( input ) - positive power for the internal analog section. agnd 13 analog ground ( input ) - ground reference for the internal analog section. filt+ 14 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. vq 15 quiescent voltage ( output ) - filter connection for internal quiescent voltage. nic 16 not internally connected - this pin is not connected internal to the device and may be connected to ground or left ?floating?. no other external connection should be made to this pin. tsto 17 test out ( output ) - this pin is an output used for test purpos es only and must be left ?floating? (no con- nection external to the pin). tsto 18 test out ( output ) - this pin is an output used for test purpos es only and must be left ?floating? (no con- nection external to the pin). tsto 19 test out ( output ) - this pin is an output used for test purpos es only and must be left ?floating? (no con- nection external to the pin). tsto 20 test out ( output ) - this pin is an output used for test purpos es only and must be left ?floating? (no con- nection external to the pin). tsto 21 22 test out ( output ) - this pin is an output used for test purpos es only and must be left ?floating? (no con- nection external to the pin). tsto 23 24 test out ( output ) - this pin is an output used for test purpos es only and must be left ?floating? (no con- nection external to the pin). reset 25 reset ( input ) - the device enters a low power mode when this pin is driven low. vl 26 digital interface power ( input ) - determines the required signal level for the serial audio interface and host control port. refer to the recommended o perating conditions for appropriate voltages. vd 27 digital power ( input ) - positive power for the internal digital section. dgnd 28 digital ground ( input ) - ground reference for the internal digital section. tsto (m/s ) 29 test out ( output ) - this pin is an output used for test purpos es only and must be left ?floating? (no con- nection external to the pin). serial port master/slave ( input/output ) - hardware mode startup option: selects between master and slave mode for the serial port. mclk 30 master clock ( input ) - clock source for t he delta-sigma modulators. sclk 31 serial clock (input/output ) - serial clock for the serial audio interface. sdin 32 serial audio data input ( input ) - input for two?s complement serial audio data. thermal pad - thermal relief pad for optimized heat dissipation. see ?qfn thermal pad? on page 59 .
8 ds723a1 cs43l21 1.1 digital i/o pin characteristics the logic level for each input should not exceed the maximum ratings for the vl power supply. pin name sw/(hw) i/o driver receiver reset input - 1.8 v - 3.3 v scl/cclk (i2s/lj ) input - 1.8 v - 3.3 v, with hysteresis sda/cdin (mclkdiv2) input/output 1.8 v - 3.3 v, cmos/open drain 1 .8 v - 3.3 v, with hysteresis ad0/cs (dem) input - 1.8 v - 3.3 v mclk input - 1.8 v - 3.3 v lrck input/output 1.8 v - 3.3 v, cmos 1.8 v - 3.3 v sclk input/output 1.8 v - 3.3 v, cmos 1.8 v - 3.3 v tsto (m/s ) input/output 1.8 v - 3.3 v, cmos 1.8 v - 3.3 v sdin input - 1.8 v - 3.3 v table 1. i/o power rails
ds723a1 9 cs43l21 2. typical connec tion diagrams 1 f +1.8 v or +2.5 v 1 f vq filt+ 0.1 f 1 f dgnd vl 0.1 f +1.8 v, +2.5 v or +3.3 v scl/cclk sda/cdin reset 2 k ? see note 1 lrck agnd ad0/cs mclk sclk 0.1 f va_hp vd sdin cs43l21 2 k ? 1 f +1.8 v or +2.5 v aoutb aouta 470 ? 470 ? c c r ext r ext see note 2 note 1 : resistors are required for i2c control port operation for best response to fs/2 : () 470 4 470 + = ext ext r fs r c this circuitry is intended for applications where the cs43l21 connects directly to an unbalanced output of the device. for internal routing applications please see the dac analog output characteristics section for loading limitations. note 2 : digital audio processor 0.1 f va headphone out left & right line level out left & right speaker driver flyp flyn vss_hp gnd_hp 1 f 51.1 ? 0.022 f 1 f ** ** * *use low esr ceramic capacitors. see note 3 note 3 : series resistance in the path of the power supplies must be avoided. any voltage drop on va_hp will directly impact the negative charge pump supply (vss_hp) and result in clipping on the audio output . 1.5 f 1.5 f see note 4 note 4 : larger capacitors, such as 1.5 f, improves the charge pump performance (and subsequent thd+n) at the full scale output power achieved with gain (g) settings greater than default. ** ** figure 1. typical connection diagram (software mode)
10 ds723a1 cs43l21 +1.8v or +2.5v 1 f vq filt+ 0.1 f 1 f dgnd vl 0.1 f +1.8v, 2.5 v or +3.3v i2s/lj mclkdiv2 reset lrck agnd dem mclk sclk 0.1 f va_hp vd sdin cs43l21 1 f +1.8v or +2.5v aoutb aouta 470 ? 470 ? c c r ext r ext see note 2 for best response to fs/2 : () 470 4 470 + = ext ext r fs r c this circuitry is intended for applications where the cs 43l21 connects directly to an unbalanced output of the device . for internal routing applications please see the dac analog output characteristics section for loading limitations . note 2 : digital audio processor 0.1 f va headphone out left & right line level out left & right speaker driver flyp flyn vss_hp gnd_hp 51.1 ? 0.022 f 1 f see note 1 note 1 : series resistance in the path of the power supplies (typically used for added filtering) must be avoided. any voltage drop on va_hp will directly impact the negative charge pump supply (vss_hp) and result in clipping on the audio output . 1 f 1 f ** ** * *use low esr ceramic capacitors. see note 3 note 3: pull-up to vl (47 k ? for master mode. pull- down to dgnd for slave mode. 47 k ? tsto/m/s vl or dgnd k ? figure 2. typical connection diagram (hardware mode)
ds723a1 11 cs43l21 3. characteristic and specification tables (all min/max characteristics and specifications are guarant eed over the specified operating conditions. typical per- formance characteristics and specifications are derived fr om measurements taken at nominal supply voltages and t a = 25 c.) specified operating conditions (agnd=dgnd=0 v, all voltages with respect to ground.) absolute maximum ratings (agnd = dgnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limit s may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. the device will operate prope rly over the full ra nge of the analog, headphone am plifier, digital core and serial/control port interface supplies. 2. any pin except supplies. transien t currents of up to 100 ma on the analog input pins will not cause scr latch-up. 3. the maximum over/under voltage is limited by the input current. parameters symbol min nom max units dc power supply (note 1) analog core va 1.65 2.37 1.8 2.5 1.89 2.63 v v headphone amplifier va_hp 1.65 2.37 1.8 2.5 1.89 2.63 v v digital core vd 1.65 2.37 1.8 2.5 1.89 2.63 v v serial/control port interface vl 1.65 2.37 3.14 1.8 2.5 3.3 1.89 2.63 3.47 v v v ambient temperature commercial - cnz automotive - dnz t a -10 -40 - - +70 +85 c c parameters symb ol min max units dc power supply analog digital serial/control port interface va, va_hp vd vl -0.3 -0.3 -0.3 3.0 3.0 4.0 v v v input current (note 2) i in -10ma digital input voltage (note 3) v ind -0.3 vl+ 0.4 v ambient operating temper ature (power applied) t a -50 +115 c storage temperature t stg -65 +150 c
12 ds723a1 cs43l21 analog output characteris tics (commercial - cnz) (test conditions (unless otherwise spec ified): input test signal is a full-scale 997 hz sine wave; measurement bandwidth is 10 hz to 20 khz; sample frequency = 48 khz; test load r l = 10 k ?, c l = 10 pf for the line output (see figure 3 ), and test load r l = 16 ?, c l = 10 pf (see figure 3 ) for the headphone output. hp_gain[2:0] = 011.) parameter (note 4) va = 2.5v (nominal) min typ max va = 1.8v (nominal) min typ max unit r l = 10 k ? dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 92 89 - - 98 95 96 93 - - - - 89 86 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -86 -75 -35 -86 -73 -33 -78 - - - - - - - - - - - -88 -72 -32 -88 -70 -30 -82 - - - - - db db db db db db r l = 16 ? dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 92 89 - - 98 95 96 93 - - - - 89 86 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -75 -75 -35 -75 -73 -33 -69 - - - - - - - - - - - -75 -72 -32 -75 -70 -30 -69 - - - - - db db db db db db other characteristics for r l = 16 ? or 10 k ? output parameters modulation index (mi) (note 5) analog gain multiplier (g) - 0.6787 0.6047 -- 0.6787 0.6047 - full-scale output voltage (2?g?mi?va) (note 5) refer to table ?line output voltage characteristics? on page 14 vpp full-scale output power (note 5) refer to table ?headphone output power characteristics? on page 15 mw interchannel isolation (1 khz) 16 ? 10 k ? - - 80 95 - - - - 80 93 - - db db interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/ c ac-load resistance (r l ) (note 6) 16 - - 16 - - ? load capacitance (c l ) (note 6) - - 150 - - 150 pf
ds723a1 13 cs43l21 analog output characteris tics (automotive - dnz) (test conditions (unless otherwise spec ified): input test signal is a full-scale 997 hz sine wave; measurement bandwidth is 10 hz to 20 khz; sample frequency = 48 khz and 96 khz; test load r l = 10 k ?, c l = 10 pf for the line output (see figure 3 ), and test load r l = 16 ?, c l = 10 pf (see figure 3 ) for the headphone output. hp_gain[2:0] = 011.) parameter (note 4) va = 2.5v (nominal) min typ max va = 1.8v (nominal) min typ max unit r l = 10 k ? dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 90 87 - - 98 95 96 93 - - - - 87 84 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -86 -75 -35 -86 -73 -33 -73 - - - - - - - - - - - -88 -72 -32 -88 -70 -30 -80 - - - - - db db db db db db r l = 16 ? dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 90 87 - - 98 95 96 93 - - - - 87 84 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -75 -75 -35 -75 -73 -33 -67 - - - - - - - - - - - -75 -72 -32 -75 -70 -30 -67 - - - - - db db db db db db other characteristics for r l = 16 ? or 10 k ? output parameters modulation index (mi) (note 5) analog gain multiplier (g) - 0.6787 0.6047 -- 0.6787 0.6047 - full-scale output voltage (2?g?mi?va) (note 5) refer to table ?line output voltage characteristics? on page 14 vpp full-scale output power (note 5) refer to table ?headphone output power characteristics? on page 15 mw interchannel isolation (1 khz) 16 ? 10 k ? - - 80 95 - - - - 80 93 - - db db interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/ c ac-load resistance (r l ) (note 6) 16 - - 16 - - ? load capacitance (c l ) (note 6) - - 150 - - 150 pf
14 ds723a1 cs43l21 line output voltage characteristics test conditions (unless otherwise specified): input test si gnal is a full-scale 997 hz sine wave; measurement band- width is 10 hz to 20 khz; sample frequency = 48 khz; test load r l = 10 k ?, c l = 10 pf (see figure 3 ). parameter va = 2.5v (nominal) min typ max va = 1.8v (nominal) min typ max unit aoutx voltage into r l = 10 k ? hp_gain[2:0] analog gain (g) va_hp 000 0.3959 1.8 v - 1.34 - - 0.97 - v pp 2.5 v - 1.34 - - 0.97 - v pp 001 0.4571 1.8 v - 1.55 - - 1.12 - v pp 2.5 v - 1.55 - - 1.12 - v pp 010 0.5111 1.8 v - 1.73 - - 1.25 - v pp 2.5 v - 1.73 - - 1.25 - v pp 011 (default) 0.6047 1.8 v - 2.05 - 1.41 1.48 1.55 v pp 2.5 v 1.95 2.05 2.15 - 1.48 - v pp 100 0.7099 1.8 v - 2.41 - - 1.73 - v pp 2.5 v - 2.41 - - 1.73 - v pp 101 0.8399 1.8 v - 2.85 - 2.05 v pp 2.5 v - 2.85 - - 2.05 - v pp 110 1.0000 1.8 v - 3.39 - - 2.44 - v pp 2.5 v - 3.39 - - 2.44 - v pp 111 1.1430 1.8 v (see (note 7) 2.79 v pp 2.5 v - 3.88 - - 2.79 - v pp
ds723a1 15 cs43l21 headphone output po wer characteristics test conditions (unless otherwise specified): input test signal is a full-scale 997 h z sine wave; measurement band- width is 10 hz to 20 khz; sample frequency = 48 khz; test load r l = 16 ?, c l = 10 pf (see figure 3 ). 4. one-half lsb of triangular pdf dither is added to data. 5. full-scale output voltage and power is determ ined by the gain setting, g, in register ?headphone analog gain (hp_gain[2:0])? on page 41 . high gain settings at certain va and va_hp supply levels may cause clipping when the audio signal approache s full-scale, maximum power output, as shown in figures 21 - 24 on page 55 . 6. see figure 3 . r l and c l reflect the recommended minimum re sistance and maximum capacitance re- quired for the internal op-amp' s stability and signal integrity. in this circuit topology, c l will effectively move the band-limiting pole of the amp in the outpu t stage. increasing this value beyond the recom- mended 150 pf can cause the internal op-amp to become unstable. 7. va_hp settings lower than va reduces the headroom of the headphone amplifier. as a result, the dac may not achieve the full thd+n performance at full-scale output voltage and power. parameter va = 2.5v (nominal) min typ max va = 1.8v (nominal) min typ max unit aoutx power into r l = 16 ? hp_gain[2:0] analog gain (g) va_hp 000 0.3959 1.8 v - 14 - - 7 - mw rms 2.5 v - 14 - - 7 - mw rms 001 0.4571 1.8 v - 19 - - 10 - mw rms 2.5 v - 19 - - 10 - mw rms 010 0.5111 1.8 v - 23 - - 12 - mw rms 2.5 v - 23 - - 12 - mw rms 011 (default) 0.6047 1.8 v (note 7) -17 -mw rms 2.5 v - 32 - - 17 - mw rms 100 0.7099 1.8 v (note 7) -23 -mw rms 2.5 v - 44 - - 23 - mw rms 101 0.8399 1.8 v (note 5) mw rms 2.5 v -32 -mw rms 110 1.0000 1.8 v (note 5 , 7 ) mw rms 2.5 v mw rms 111 1.1430 1.8 v mw rms 2.5 v mw rms aoutx agnd r l c l 0.022 f 51 ? figure 3. headphone output test load
16 ds723a1 cs43l21 combined dac interp olation & on-chip ana log filter response notes: 8. response is clock dependent and will scale with fs. note that the response plots ( figure 27 to figure 30 on page 60 ) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 9. measurement bandwidth is from stopband to 3 fs. switching specificat ions - serial port (inputs: logic 0 = dgnd, logic 1 = vl.) parameter (note 8) min typ max unit frequency response 10 hz to 20 khz -0.01 - +0.08 db passband to -0.05 db corner to -3 db corner 0 0 - - 0.4780 0.4996 fs fs stopband 0.5465 - - fs stopband attenuation (note 9) 50 - - db group delay - 10.4/fs - s de-emphasis error fs = 32 khz fs = 44.1 khz fs = 48 khz - - - - - - +1.5/+0 +0.05/-0.25 -0.2/-0.4 db db db parameters symbol min max units reset pin low pulse width (note 10) 1-ms mclk frequency 1.024 38.4 mhz mclk duty cycle (note 11) 45 55 % slave mode input sample rate (lrck) quarter-speed mode half-speed mode single-speed mode double-speed mode f s f s f s f s 4 8 4 50 12.5 25 50 100 khz khz khz khz lrck duty cycle 45 55 % sclk frequency 1/t p -64?f s hz sclk duty cycle 45 55 % lrck setup time before sclk rising edge t s(lk-sk) 40 - ns sdin setup time before sclk rising edge t s(sd-sk) 20 - ns sdin hold time after sclk rising edge t h 20 - ns
ds723a1 17 cs43l21 10. after powering up the cs43l21 , reset should be held low after the power supplies and clocks are set- tled. 11. see ?example system clock frequencies? on page 57 for typical mclk frequencies. 12. see ?master? on page 29 master mode (note 12) output sample rate (lrck) all speed modes f s -hz lrck duty cycle 45 55 % sclk frequency 1/t p - 64?f s hz sclk duty cycle 45 55 % lrck edge to sdin msb rising edge t d(msb) 52 ns sdin setup time before sclk rising edge t s(sd-sk) 20 - ns sdin hold time after sclk rising edge t h 20 - ns parameters symbol min max units // // // // // // t s(sd-sk) msb msb-1 lrck sclk sdin t s(lk-sk) t p t h figure 4. serial audio interface slave mode timing mclk 128 ----------------- // // // // // // t s(sd-sk) msb msb-1 lrck sclk sdin t d(msb) t p t h figure 5. serial audio interface master mode timing
18 ds723a1 cs43l21 switching specifi cations - i2c ? control port (inputs: logic 0 = dgnd, logic 1 = vl, sda c l =30pf) 13. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz reset rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 13) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc -1s fall time scl and sda t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 3450 ns t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 6. control port timing - i2c
ds723a1 19 cs43l21 switching charact eristics - spi ? control port (inputs: logic 0 = dgnd, logic 1 = vl) 14. data must be held for sufficient time to bridge the transition time of cclk. 15. for f sck <1 mhz. parameter symbol min max units cclk clock frequency f sck 06.0mhz reset rising edge to cs falling t srs 20 - ns cs falling to cclk edge t css 20 - ns cs high time between transmissions t csh 1.0 - s cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 14) t dh 15 - ns rise time of cclk and cdin (note 15) t r2 -100ns fall time of cclk and cdin (note 15) t f2 -100ns cs cclk cdin rst t srs t scl t sch t css t r2 t f2 t csh t dsu t dh figure 7. control po rt timing - spi format
20 ds723a1 cs43l21 dc electrical characteristics (agnd = 0 v; all voltages with respect to ground.) 16. the dc current draw represents the allowed current draw from the vq pin due to typical leakage through electrolytic de-coupling capacitors. 17. valid with the recommended capacitor values on filt+ and vq. increasing the capacitance will also increase the psrr. digital interface specific ations & characteristics 18. see ?digital i/o pin characteristics? on page 8 for serial and control port power rails. parameters min typ max units vq characteristics nominal voltage output impedance dc current source/sink (note 16) - - - 0.5?va 23 - - - 10 v k ? a filt+ -va-v vss_hp characteristics nominal voltage dc current source - - -0.8?(va_hp) - 10 v a power supply rejection ratio (psrr) (note 17) 1 khz -60-db parameters (note 18) symbol min max units input leakage current i in -10 a input capacitance -10pf 1.8 v - 3.3 v logic high-level output voltage (i oh = -100 a) v oh vl - 0.2 - v low-level output voltage (i ol = 100 a) v ol -0.2v high-level input voltage v ih 0.68?vl - v low-level input voltage v il - 0.32?vl v
ds723a1 21 cs43l21 power consumption see (note 19) 19. unless otherwise noted, test conditions are as follows: all zeros input, sl ave mode, sample rate = 48 khz; no load. digital (vd) and logic (vl) supply current will vary depending on speed m ode and mas- ter/slave operation. 20. reset pin 25 held lo, all clocks and data lines are held lo. 21. reset pin 25 held hi, all clocks and data lines are held hi. 22. vl current will slightly in crease in master mode. power ctl. registers typical current (ma) operation 02h 03h pdn_dacb pdn_daca bit 4 bit 3 bit 2 bit 1 pdn bit 3 bit 2 bit 1 v i va_hp i va i vd i vl (note 22) total power (mw rms ) 1 off (note 20) xxxxxxxxxx 1.8 0 0 0 0 0 2.5 0 0 0 0 0 2 standby (note 21) xxxxxx1xxx 1.8 0 0.01 0.02 0 0.05 2.5 0 0.01 0.03 0 0.10 5 mono playback 1011110111 1.8 1.66 1.40 2.35 0.01 9.74 2.5 2.03 1.71 3.48 0.02 18.08 6 stereo playback 0011110111 1.8 2.77 2.05 2.35 0.01 12.93 2.5 3.21 2.50 3.49 0.02 23.02
22 ds723a1 cs43l21 4. applications 4.1 overview 4.1.1 architecture the cs43l21 is a highly integrated, low power, 24-bit audio d/a comprised of stereo digital-to-analog converters (dac) designed using multi-bit delta-sigma techniques. the dac operates at an oversampling ratio of 128fs. the d/a operates in one of four samp le rate speed modes: quarter, half, single and dou- ble. it accepts and is capable of generating serial po rt clocks (sclk, lrck) derived from an input master clock (mclk). 4.1.2 line & headphone outputs the analog output portion of the d/a includes a he adphone amplifier capable of driving headphone and line-level loads. an on-chip charge pump creates a negative headphone supply allowing a full-scale out- put swing centered around ground. this eliminates the need for large dc-blocking capacitors and allows the amplifier to deliver more power to headphone loads at lower supply voltages. eight gain settings for the headphone amplifier are available. 4.1.3 signal processing engine a signal processing engine is available to process serial input d/a data before output to the dac. the d/a data has independent volume controls and mixing functions such as mono mixes and left/right chan- nel swaps. a tone control provides bass and treble at four selectable corner frequencies. an automatic level control provides limiting capabilities at programmable attack and release rates, maximum thresholds and soft ramping. a 15/50 s de-emphasis filter is also available at a 44.1 khz sample rate. 4.1.4 beep generator a beep may be generated internally at select freq uencies across approximately two octave major scales and configured to occur continuously, periodically or at single time intervals controlled by the user. volume may be controlled independently. 4.1.5 device control (hardw are or software mode) in software mode, all functions and features may be controlled via a two-wire i2c or three-wire spi control port interface. in hardware mode, a limited feature set may be controlled via stand-alone control pins. 4.1.6 power management two software mode control registers provide independent power-down control of the dac, allowing op- eration in select applications with minimal power consumption.
ds723a1 23 cs43l21 4.2 hardware mode a limited feature-set is available when the d/a powers up in ha rdware mode (see ?recommended power- up sequence? section on page 31 ) and may be controlled via stand-alone control pins. table 2 shows a list of functions/features, the defaul t configuration and the associated stand-alone control available. hardware mode feature/function summary feature/function default configuration stand-alone control note power control device dacx powered up powered up -- auto-detect enabled - - speed mode serial port slave serial port master auto-detect speed mode single-speed mode -- mclk divide (selectable) ?mclkdiv2? pin 2 see section 4.4 on page 28 serial port master / slave selection (selectable) ?m/s ? pin 29 see section 4.4 on page 28 interface control dac (selectable) ?i2s/lj ? pin 3 see section 4.5 on page 30 dac volume & gain hp gain aoutx volume invert soft ramp zero cross g = 0.6047 0 db disabled enabled disabled -- dac de-emphasis (selectable) ?dem? pin 4 see section on page 24 signal processing engine (spe) mix beep tone control peak detect and limiter disabled disabled disabled disabled -- data selection data input (pcm) to dac - - channel mix dac pcma = l; pcmb = r - - charge pump frequency (64xfs)/7 - - table 2. hardware mode feature summary
24 ds723a1 cs43l21 4.3 analog outputs aouta and aoutb are the ground-centered line or he adphone outputs. various signal processing options are available, including an internal beep generator. the desired path to the dac must be selected using the data_sel[1:0] bits. 4.3.1 de-emphasis filter the codec includes on-chip digital de-emphasis optimiz ed for a sample rate of 44.1 khz. the filter re- sponse is shown in figure 9 . the de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of nois e reduction. de-emphasis is only available in single-speed mode. software controls: ?dac control (address 09h)? on page 42 . software controls: ?dac control (address 09h)? on page 42 . hardware control: pin setting selection ?dem? pin 4. lo no de-emphasis hi de-emphasis applied charge pump left/right hp out switched capacitor dac and filter headphone amp - gnd centered pdn_daca pdn_dacb data_sel[1:0] 00 chrg_freq[3:0] 01 hp_gain[2:0] beep generator bass/ treble/ control vol peak detect limiter chnl vol. settings demph vol vol +12db/-102db 0.5db steps outa_vol[7:0] outb_vol[7:0] +12db/-51.5db 0.5db steps pcmmixa_vol[6:0] pcmmixb_vol[6:0] 0db/-50db 2.0db steps bpvol[4:0] mute_pcmmixa mute_pcmmixb deemph bass[3:0] treb[3:0] +12.0db/-10.5db 1.5db steps bass_cf[1:0] treb_cf[1:0] tc_en signal processing engine (spe) dac_szc[1:0] daca_mute dacb_mute inv_daca inv_dacb dac_sngvol amute arate[7:0] rrate[7:0] max[2:0] min[2:0] lim_srdis lim_zcdis limit_en pcma[1:0] pcmb[1:0] pcm serial interface offtime[2:0] ontime[3:0] freq[3:0] repeat beep channel swap figure 8. output architecture
ds723a1 25 cs43l21 4.3.2 volume controls two digital volume control functions offer independen t control of the sdin signal path into the mixer as well as a combined control of the mixed signals. the volume controls are programmable to ramp in incre- ments of 0.125 db at a rate controlled by the soft ramp/zero cross settings. the signal paths may also be muted via mute contro l bits. when enabled, each bit attenuates the signal to its maximum value. when the mute bit is disabled, the signal returns to the attenuation level set in the respective volume control register . the attenuation is ramped up and do wn at the rate specified by the dac_szc[1:0] bits. 4.3.3 mono channel mixer a channel mixer may be used to create a mix of the left and right channels for the sdin data. this mix allows the user to produce a mono signal from a stereo source. the mixer may also be used to imple- ment a left/right channel swap. 4.3.4 beep generator the beep generator generates audio frequencies acro ss approximately two octave major scales. it offers three modes of operation: continuous, multiple a nd single (one-shot) beeps. sixteen on and eight off times are available. note: the beep is generated before the limiter and may affect desired limiting performance. if the limiter function is used, it may be required to set the beep volume sufficiently below the threshold to prevent the peak detect from triggeri ng. since the master volume control, aoutx_vol[7:0 ], will affect the beep vol- ume, dac volume may altern atively be controlled using the pcmmixx_vol[6:0] bits. software controls: ?pcmx mixer volume control: pcma (address 10h) & pcmb (address 11h)? on page 44?aoutx volume control: aouta (address 16h) & aoutb (address 17h)? on page 49?dac output control (address 08h)? on page 41 software controls: ?pcm channel mixer (a ddress 18h)? on page 49 . software controls: ?beep frequency & timing configuration (address 12h)? on page 45 , ?beep off time & volume (address 13h)? on page 46 , ?beep configuration & tone configuration (address 14h)? on page 47 gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 9. de-emphasis curve
26 ds723a1 cs43l21 4.3.5 tone control shelving filters are used to implement bass and treble (boost and cut) with four selectable corner frequen- cies. boosting will affect peak detect and limiting wh en levels exceed the ma ximum threshold settings. 4.3.6 limiter when enabled, the limiter monitors the digital input signal before the dac modulator, detects when levels exceed the maximum threshold settings and lowers the aout volume at a programmable attack rate be- low the maximum threshold. when the input signal level falls below the maxi mum threshold, the aout volume returns to its origin al level set in the volume control register at a programmable release rate. at- tack and release rates are affected by the dac soft ra mp/zero cross settings and sample rate, fs. limiter soft ramp and zero cross dependency may be independently enabled/disabled. recommended settings : best limiting performance may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. the ?cushion? bits allow the user to set a threshold slightly below the maximum threshold for hyst eresis control - this cushions the sound as the lim- iter attacks and releases. note: 1. when the limiter is enabled, the aout volume is automatically controlled and should not be adjusted manually. alternative volume control may be realized using the pcmmixx_vol[6:0] bits. 2. the limiter maintains the output signal between the cush and max thresholds. as the digital input signal level changes, the level-co ntrolled output may not always be th e same but will always fall within the thresholds. software controls: ?tone control (address 15h)? on page 48 . software controls: ?limiter release rate register (address 1ah)? on page 51 , ?limiter attack rate register (address 1bh)? on page 52 , ?dac control (address 09h)? on page 42 freq[3:0] ... bpvol[4:0] ontime[3:0] offtime[2:0] repeat = '0' beep = '1' repeat = '1' beep = '0' repeat = '1' beep = '1' single-beep : beep turns on at a configurable frequency (freq) and volume (bpvol) for the duration of ontime. beep must be cleared and set for additional beeps. multi-beep : beep turns on at a configurable frequency (freq) and volume (bpvol) for the duration of ontime and turns off for the duration of offtime. on and off cycles are repeated until repeat is cleared. continuous beep : beep turns on at a configurable frequency (freq) and volume (bpvol) and remains on until repeat is cleared. figure 10. beep configuration options
ds723a1 27 cs43l21 4.3.7 line-level outputs and filtering the codec contains on-chip buffer amplifiers capable of producing line level single-ended outputs on aouta and aoutb. these amplifiers are ground center ed and do not have any dc offset. a load stabi- lizer circuit, shown in the ?typical connection diagram (software mode)? on page 9 and the ?typical con- nection diagram (hardware mode)? on page 10 , is required on the analog ou tputs. this allows the dac amplifiers to drive line or headphone outputs. also shown in the typical connection diagrams is th e recommended passive output filter to support high- er impedances such as those found on the inputs to operational amplif iers. ?rext?, shown in the typical connection diagrams, is the input impedance of the receiving device. the invert and digital gain controls may be used to provide phase and/or amplitude compensation for an external filter. the delta-sigma conversion process produces high fr equency noise beyond the audio passband, most of which is removed by the on-chip analog filters. th e remaining out-of-band noise can be attenuated using an off-chip low pass filter. software controls: ?dac output control (address 08h)? on page 41 , ?aoutx volume control: aouta (address 16h) & aoutb (address 17h)? on page 49 . max[2:0] output (after limiter) input rrate[5:0] arate[5:0] volume limiter cush[2:0] attack/release sound cushion max[2:0] aoutx_vol[7:0] volume control should not be adjusted manually when limiter is enabled. figure 11. peak detect & limiter
28 ds723a1 cs43l21 4.3.8 on-chip charge pump an on-chip charge pump derives a negative supply vo ltage from the va_hp supply. this provides dual rail supplies allowing a full-scale output swing centered around ground and eliminates the need for large, dc-blocking capacitors. added benefits include grea ter pop suppression and improved low frequency (bass) response. note: series resistance in the path of the power supplies must be avoided. any voltage drop on the va_hp supply will directly impact the derived negative volt age on the charge pump supply, vss_hp, and may result in clipping. the flyn and flyp pins connect to internal switches that charges and discharges the external capacitor attached, at a default switching frequency. this freq uency may be adjusted in the control port registers. increasing the charge-pumpi ng capacitor will slightly decease the pumping freque ncy. the capacitor con- nected to vss_hp acts as a charge reservoir for the n egative supply as well as a filter for the ripple in- duced by the charge pump. increasing this capacitor will decrea se the ripple on vss_hp. refer to the typical connection diagrams in figure 1 on page 9 or figure 2 on page 10 for the recomm ended capacitor values for the charge pump circuitry. 4.4 serial port clocking the d/a serial audio interface port operates either as a slave or ma ster. it accepts externally generated clocks in slave mode an d will generate synchronous clocks derived from an input master clock (mclk) in master mode. the frequency of the mclk must be an integer multip le of, and synchronous with, the system sample rate, fs. the lrck frequency is equal to fs, the frequency at which audio samples for each channel are clocked into or out of the device. the speed and mclkdiv2 software control bits or the m/s and mclkdiv2 stand-alone control pins, con- figure the device to generate the proper clocks in ma ster mode and receive the proper clocks in slave mode. the value on the m/s pin is latched immediately after powering up in hardware mode. software controls: ?charge pump frequency (address 21h)? on page 53 . software control: , ?dac control (address 09h)? on page 42 . hardware control: pin setting selection ?m/s ? pin 29 47 k ? pull-down slave 47 k ? pull-up master ?mclkdiv2? pin 2 lo no divide hi mclk is divided by 2 prior to all internal circuitry.
ds723a1 29 cs43l21 4.4.1 slave lrck and sclk are inputs in slave mode. the spee d of the d/a is automatically determined based on the input mclk/lrck ratio when the auto-detec t function is enabled. certai n input clock ratios will then require an internal divide-by-two of mclk* using ei ther the mclkdiv2 bit or the mclkdiv2 stand-alone control pin. additional clock ratios are allowed when the auto-det ect function is disabled; but the appropriate speed mode must be selected us ing the speed[1:0] bits. 4.4.2 master lrck and sclk are internally derived from the internal mclk (after the divide, if mclkdiv2 is enabled). in hardware mode the d/a operates in single-speed only. in software mode, the d/a operates in either quarter-, half-, si ngle- or double-speed de pending on the setting of the speed[1:0] bits. auto-detect qsm hsm ssm dsm disabled (software mode only) 512, 768, 1024, 1536, 2048, 3072 256, 384, 512, 768, 1024, 1536 128, 192, 256, 384, 512, 768 128, 192, 256, 384 enabled 1024, 1536, 2048*, 3072* 512, 768, 1024*, 1536* 256, 384, 512*, 768* 128, 192, 256*, 384* *mclkdiv2 must be enabled. table 3. mclk/lrck ratios 256 128 512 lrck output (equal to fs) single speed quarter speed half speed 01 10 11 sclk output 2 1 0 1 mclk mclkdiv2 128 00 4 2 8 single speed quarter speed half speed 01 10 11 2 00 double speed double speed speed[1:0] figure 12. master mode timing
30 ds723a1 cs43l21 4.4.3 high-impedance digital output the serial port may be placed on a clock/data bus th at allows multiple mast ers for the sclk/lrck i/o without the need for external buffers. the 3st_sp bit places the internal buffers for these i/o in a high- impedance state, allowing another device to transmit clocks without bus contention. 4.4.4 quarter- and half-speed mode quarter-speed mode (qsm) and half-speed mode (h sm) allow lower sample ra tes while maintaining a relatively flat noise floo r in the typical audio band of 20 hz - 20 khz. single-spee d mode (ssm) will allow lower frequency sample rates; however, the dac's noise floor, that normally rises out-of -band, will scale with the lower sample rate and begin to rise within the audio band. qsm and hsm corrects for most of this scaling, effectively increasing the dynamic rang e of the codec at lower sa mple rates, relative to ssm. 4.5 digital interface formats the serial port operates in standard i2 s, left-justified or right-justifieddi gital interface formats with varying bit depths from 16 to 24. data is clocked into the dac on the rising edge of sclk. figures 14 - 17 illustrate the general structure of each format. refer to ?switching specifications - serial port? on page 16 for exact timing relationship between clocks and data. software control: ?interface control (address 04h)? on page 41 . hardware control: pin setting selection ?i2s/lj ? pin 3 lo left-justified interface hi i2s interface cs42l51 transmitting device #1 transmitting device #2 receiving device 3st_sp sclk/lrck figure 13. tri-state sclk/lrck lrck sclk msb lsb msb lsb aouta / ainxa left channel right channel sdin aoutb / ainxb msb figure 14. i2s format
ds723a1 31 cs43l21 4.6 initialization the initialization and power-down se quence flowchart is shown in figure 17 on page 32 . the codec en- ters a power-down state upon initial power-up. the in terpolation and decimation filters, delta-sigma modu- lators and control port registers are reset. the internal voltage reference, multi-bit dac and switched- capacitor low-pass filters are powered down. the device will remain in the power-down state until the reset pin is brought high. the control port is ac- cessible once reset is high and the desired register settings can be loaded per the interface descriptions in ?software mode? on page 33 . if a valid write sequence to the cont rol port is not made within approximately 10 ms, the will ente r hardware mode. once mclk is valid, the quiescent voltage, vq, an d the internal voltage refe rences, filt+ will begin pow- ering up to normal operation. the charge pump slow ly powers up and charges the capacitors. power is then applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut- ed state. once lrck is valid, mclk occurrences are counted over one lrck period to determine the mclk/lrck frequency ratio and normal operation begins. 4.7 recommended power-up sequence 1. hold reset low until the power supplies are stable. 2. bring reset high. after approximately 10 ms, the device will enter hardware mode. 3. for software mode operation, set t he pdn bit to ?1?b in un der 10 ms. this will plac e the device in ?stand- by?. 4. load the desired register settings wh ile keeping the pdn bit set to ?1?b. 5. start mclk to the appropriat e frequency, as discussed in section 4.4 . 6. set the pdn bit to ?0?b. 7. apply lrcksclk and sdin for normal operation to begin. 8. bring reset low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. lrck sclk msb lsb msb lsb left channel right channel sdin msb aouta / ainxa aoutb / ainxb figure 15. left-justified format lrck sclk msb lsb msb lsb left channel right channel sdin aouta aoutb figure 16. right-justi fied format (dac only)
32 ds723a1 cs43l21 4.8 recommended power-down sequence to minimize audible pops when turning off or placing the d/a in standby, 1. mute the dac?s. 2. set the pdn bit in the power control register to ?1 ?b. the d/a will not power down until it reaches a fully muted sate. do not re move mclk until after the part has fully muted. note that it may be necessary to disable the soft ramp and/or zero cross volume transitions to achieve fa ster muting/power down. 3. bring reset low. initialization software mode registers setup to desired settings. reset = low? no power 1. no audio signal generated. off mode (power applied) 1. no audio signal generated. 2. control port registers reset to default. control port active control port valid write seq. within 10 ms? hardware mode minimal feature set support. pdn bit = '1'b? sub-clocks applied 1. lrck valid. 2. sclk valid. 3. audio samples processed. valid mclk/lrck ratio? no yes no yes no yes yes no normal operation audio signal generated per control port or stand- alone settings. analog output freeze 1. aout bias = last audio sample. 2. dac modulators stop operation. 3. audible pops. error: mclk removed pdn bit set to '1'b (software mode only) standby mode 1. no audio signal generated. 2. control port registers retain settings. reset transition 1. pops suppressed. power off transition 1. audible pops. error: power removed valid mclk applied? no 20 ms delay charge caps 1. vq charged to quiescent voltage. 2. filtx+ charged. digital/analog output muted 50 ms delay charge pump powered up headphone amp powered up 20 s delay headphone amp powered down 20 s delay stand-by transition 1. pops suppressed. error: mclk/lrck ratio change reset = low figure 17. initialization flow chart
ds723a1 33 cs43l21 4.9 software mode the control port is used to access the registers allowin g the d/a to be configured for the desired operational modes and formats. the operation of the control port may be completely asynchronous with respect to the audio sample rates. however, to av oid potential interference problems, the control port pins should remain static if no operation is required. the control port operates in two modes: spi and i2c, with the d/a acting as a slave device. software mode is selected if there is a high-to-low transition on the ad0/cs pin after the reset pin has been brought high. i2c mode is selected by connecting the ad0/cs pin through a resistor to vl or dgnd, thereby permanently selecting the desired ad0 bit address state. 4.9.1 spi control in software mode, cs is the cs43l21 chip-select signal, cclk is the control port bit clock (input into the from the microcontroller), cdin is th e input data line from the microcontr oller. data is clocked in on the rising edge of cclk. the d/a will only support write operations. read re quest will be ignored. figure 18 shows the operation of the control port in software mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and must be 1001010. the eighth bit is a read/write indicator (r/w ), which should be low to writ e. the next eight bits form t he memory address pointer (map), which is set to the address of the r egister that is to be updated. the ne xt eight bits are the data which will be placed into the register designated by the map. there is map auto-increment capability, enabled by the incr bit in the map register. if incr is a zero, the map will stay constant for successive read or writ es. if incr is set to a 1, the map will auto-increment after each byte is read or wr itten, allowing block reads or wr ites of successive registers. 4.9.2 i2c control in i2c mode, sda is a bidirectional da ta line. data is clocked into and out of the part by the clock, scl. there is no cs pin. pin ad0 forms the least significant bi t of the chip address and should be connected through a resistor to vl or dgnd as desired. the state of the pin is sensed while the cs43l21 is being reset. the signal timings for a read and write cycle are shown in figure 19 and figure 20 . a start condition is defined as a falling transition of sda while the clock is high. a stop co ndition is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the cs43l21 after a start condition consists of a 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper 6 bits of the 7-bit address field are fixed at 100101. to communicate with a cs43l21 , the chip address field, which is the first byte sent to the cs43l21 , should match 100101 followed by the setting of the ad0 pin. the ei ghth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address poin ter (map) which selects the register to be read or written. if the op- eration is a read, the conten ts of the register pointe d to by the map will be outp ut. setting the auto-incre- 4 5 6 7 cclk chip address (write) map byte data 1 0 0 1 0 1 0 0 cdin incr 6 5 4 3 2 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 10 11 13 14 15 data +n cs 7 6 1 0 figure 18. control port timing in spi mode
34 ds723a1 cs43l21 ment bit in map allows successive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the cs43l21 after each input byte is read and is input to the cs43l21 from the microcontroller after each transmitted byte. since the read operation cannot set the map, an aborte d write operation is used as a preamble. as shown in figure 20 , the write operation is aborted after the acknowledge for the map byte by sending a stop con- dition. the following pseudocode illu strates an aborted wr ite operation followed by a read operation. send start condition. send 100101x0 (chip address & write operation). receive acknowledge bit. send map byte, auto-increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 100101x1 (chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto-increment bit in the map allows succe ssive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 19. control port timing, i2c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 1 ad0 0 sda 1 0 0 1 0 1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 20. control port timing, i2c read
ds723a1 35 cs43l21 4.9.3 memory address pointer (map) the map byte comes after the address byte and selects the register to be read or written. refer to the pseudo code above for implementation details. 4.9.3.1 map increment (incr) the device has map auto-increment capability enabled by the incr bit (the msb) of the map. if incr is set to 0, map will stay constant for successive i2c writes or reads and spi writes. if incr is set to 1, map will auto-increment after each byte is read or written, allowing block reads or writ es of successive registers.
36 ds723a1 cs43l21 5. register qu ick reference software mode register defaults are as shown. ?res erved? registers must maintain their default state. addrfunction7 6543210 01h id chip_id4 chip_id3 chip_id2 chip_id1 chip_id0 rev_id2 rev_id1 rev_id0 p39 default 1 1011001 02h power ctl. 1 reserved pdn_dacb pdn_daca reserve d reserved reserved reserved pdn p39 default 0 00 1(see note 2 on page 39 ) 1(see note 2 on page 39 ) 1(see note 2 on page 39 ) 1(see note 2 on page 39 ) 0 03h speed ctl. & power ctl. 2 auto speed1 speed0 3-st_sp reserved reserved reserved mclkdiv2 p40 default 1 0101110 04h interface ctl. reserved m/s dac_dif2 dac_dif1 dac_dif0 reserved reserved reserved p41 default 0 0000000 05h reserved reserved reserved reserved rese rved reserved reserved reserved reserved default 0 0000000 06h reserved reserved reserved reserved rese rved reserved reserved reserved reserved default 1 0100000 07h reserved reserved reserved reserved rese rved reserved reserved reserved reserved default 0 0000000 08h dac output control hp_gain2 hp_gain1 hp_gain0 dac_sng vol inv_pcmb inv_pcma dacb_ mute daca_ mute p41 default 0 1100000 09h dac control data_sel1 data_sel0 freeze reserved deemph amute dac_szc1 dac_szc0 p42 default 0 0000110 0ah reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0000000 0bh reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0000000 0ch reserved reserved reserved reserved rese rved reserved reserved reserved reserved default 0 0000000 0dh reserved reserved reserved reserved rese rved reserved reserved reserved reserved default 0 0000000 0eh reserved reserved reserved reserved rese rved reserved reserved reserved reserved default 1 0000000
ds723a1 37 cs43l21 0fh reserved reserved reserved reserved rese rved reserved reserved reserved reserved default 1 0000000 10h vol. control pcmmixa mute_pcm mixa pcmmixa vol6 pcmmixa vol5 pcmmixa vol4 pcmmixa vol3 pcmmixa vol2 pcmmixa vol1 pcmmixa vol0 p44 default 1 0000000 11h vol. control pcmmixb mute_pcm mixb pcmmixb vol6 pcmmixb vol5 pcmmixb vol4 pcmmixb vol3 pcmmixb vol2 pcmmixb vol1 pcmmixb vol0 p44 default 1 0000000 12h beep freq. & ontime freq3 freq2 freq1 freq0 ontime3 ontime2 ontime1 ontime0 p45 default 0 0000000 13h beep off time & vol offtime2 offtime1 offtime0 bpvol4 bpvol3 bpvol2 bpvol1 bpvol0 p46 default 0 0000000 14h beep con- trol & tone config repeat beep reserved treb_cf1 treb_cf0 ba ss_cf1 bass_cf0 tc_en p47 default 0 0000000 15h tone control treb3 treb2 treb1 treb0 bass3 bass2 bass1 bass0 p48 default 1 0001000 16h vol. control aouta aouta_ vol7 aouta_ vol6 aouta_ vol5 outa_ vol4 aouta_ vol3 aouta_ vol2 aouta_ vol1 aouta_ vol0 p49 default 0 0000000 17h vol. control aoutb aoutb_ vol7 aoutb_ vol6 aoutb_ vol5 aoutb_ vol4 aoutb_ vol3 aoutb_ vol2 aoutb_ vol1 aoutb_ vol0 p49 default 0 0000000 18h pcm channel mixer pcma1 pcma0 pcmb1 pcmb0 reserved reserved reserved reserved p49 default 0 0000000 19h limiter threshold & szc disable max2 max1 max0 cush2 cush1 cush0 lim_srdis lim_zcdis p50 default 0 0000000 1ah limiter con- fig & release rate limit_en limit_all lim_rrate 5 lim_rrate 4 lim_rrate 3 lim_rrate 2 lim_rrate 1 lim_rrate 0 p51 default 0 1111111 1bh limiter attack rate reserved reserved lim_arate5 lim_arate4 lim_arate3 lim_arate2 lim_arate1 lim_arate0 p52 default 0 0000000 1ch reserved reserved reserved reserved reserved reserved reserved reserved reserved addrfunction7 6543210
38 ds723a1 cs43l21 default 0 0000000 1dh reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0111111 1eh reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0000000 1fh reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0000000 20h status reserved sp_clker r speb_ovfl spea_ovfl pcma_ovfl pcmb_ovfl reserved reserved p52 default 0 0000000 21h chrg_ freq3 chrg_ freq2 chrg_ freq1 chrg_ freq0 reserved reserved reserved reserved p53 default 0 1010000 addrfunction7 6543210
ds723a1 39 cs43l21 6. register description all registers are read/write except for the chip i.d. and revision register and interrupt status register which are read only. see the following bit definition tables for bit assi gnment information. the default state of each bit after a power-up sequence or reset is lis ted in each bit description. all ?reserved? registers must maintain their default state. 6.1 chip i.d. and revision regist er (address 01h) (read only) chip i.d. (chip_id[4:0]) default: 11011 function: i.d. code for the cs43l21. permanently set to 11011. chip revision (rev_id[2:0]) default: 001 function: cs43l21 revision level. revision b is co ded as 001. revision a is coded as 000. 6.2 power control 1 (address 02h) notes: 1. to activate the power-down sequence for individual channels (a or b,) both channels must first be pow- ered down either by enabling the pdn bit or by enabling the power-down bits for both channels. en- abling the power-down bit on an in dividual channel basis after the d/a has fully powered up will mute the selected channel without achieving any power savings. 2. reserved bits 1 - 4 should always be set ?high? by the user to minimize power consumption during nor- mal operation. recommended channel power-down sequence : 1.) enable the pdn bit, 2.) enable power-down for the se- lect channels, 3.) disable the pdn bit. power down dac x (pdn_dacx) default: 0 0 - disable 1 - enable function: dac channel x will either enter a power-down or muted state when this bit is enabled. see note 1 above. 76543210 chip_id4 chip_id3 chip_id2 chip_id1 chip_id0 rev_id2 rev_id1 rev_id0 76543210 reserved pdn_dacb pdn_daca reserved reserved reserved reserved pdn
40 ds723a1 cs43l21 power down (pdn) default: 0 0 - disable 1 - enable function: the entire d/a will enter a low-power st ate when this function is enabled. the contents of the control port registers are retained in this mode. 6.3 speed control (address 03h) auto-detect speed mode (auto) default: 1 0 - disable 1 - enable function: enables the auto-detect circuitry for detecting the spe ed mode of the d/a when operating as a slave. when auto is enabled, the mclk/lrck ratio must be implemented according to table 3 on page 29 . the speed[1:0] bits are ignored when this bit is enabled. speed is determined by th e mclk/lrck ratio. speed mode (speed[1:0]) default: 01 11 - quarter-speed mode (qsm) - 4 to 12.5 khz sample rates 10 - half-speed mode (hsm) - 12.5 to 25 khz sample rates 01 - single-speed mode (ssm) - 4 to 50 khz sample rates 00 - double-speed mode (dsm) - 50 to 100 khz sample rates function: sets the appropriate speed mode for the d/a in mast er or slave mode. qsm is optimized for 8 khz sample rate and hsm is optimized for 16 khz sample rate. these bits are ignored when the auto bit is enabled (see auto-detect speed mode (auto) above). tri-state serial port interface (3st_sp) default: 0 0 - disable 1 - enable function: when enabled and the device is configured as a ma ster, the sclk/lrck signals are placed in a high-im- pedance output state. if the serial port is configured as a slav e, sclk/lrck are configured as inputs. mclk divide by 2 (mclkdiv2) default: 0 0 - disabled 1 - divide by 2 76543210 auto speed1 speed0 3-st_sp reserved reserved reserved mclkdiv2
ds723a1 41 cs43l21 function: divides the input mclk by 2 prior to all internal circui try. this bit is ignored when the auto bit is disabled in slave mode. 6.4 interface cont rol (address 04h) master/slave mode (m/s ) default: 0 0 - slave 1 - master function: selects either master or slave operation for the serial port. dac digital interface format (dac_dif[2:0]) default = 000 function: selects the digital interface format used for the data in on sdin. the required relationship between the left/right clock, serial clock and serial data is define d by the digital interface format and the options are detailed in the section ?digital interface formats? on page 30 . 6.5 dac output control (address 08h) headphone analog gain (hp_gain[2:0]) default: 011 76543210 reserved m/s dac_dif2 dac_dif1 dac_dif0 reserved reserved reserved dac_dif[2:0] description figure 000 left-justified, up to 24-bit data 15 on page 31 001 i2s, up to 24-bit data 14 on page 30 010 right-justified, 24-bit data 17 on page 3217 on page 32 011 right-justified, 20-bit data 17 on page 3217 on page 32 100 right-justified, 18-bit data 17 on page 3217 on page 32 101 right-justified, 16-bit data 17 on page 3217 on page 32 110 reserved - 100 reserved - 76543210 hp_gain2 hp_gain1 hp_gain0 dac_ sngvol inv_pcmb inv_pcma dacb_mute daca_mute hp_gain[2:0] gain setting 000 0.3959 001 0.4571 010 0.5111 011 0.6047 100 0.7099 101 0.8399 110 1.0000 111 1.1430
42 ds723a1 cs43l21 function: these bits select the gain multiplie r for the headphone/line outputs. see ?line output voltage characteris- tics? on page 14 and ?headphone output power characteristics? on page 15 . dac single volume control (dac_sngvol) default: 0 function: the individual channel volume levels are independently controlled by th eir respective volume control reg- isters when this function is disabled. when enabled, the volume on all channels is determined by the aou- ta volume control register and the aoutb volume control register is ignored. pcmx invert signal polarity (inv_pcmx) default: 0 0 - disabled 1 - enabled function: when enabled, this bit will invert the signal polarity of the pcm x channel. dacx channel mute (dacx_mute) default: 0 0 - disabled 1 - enabled function: the output of channel x dac will mute when enabled. the muting function is affected by the dacx soft and zero cross bits (dacx_szc[1:0]). 6.6 dac control (address 09h) dac data selection (data_sel[1:0]) default : 00 00 - pcm serial port to dac 01 - signal processing engine to dac 10 - reserved 11 - reserved function: selects the digital signal source for the dac. note: certain functions are only available when the ?signal processing engine to dac? option is selected using these bits. 76543210 data_sel1 data_sel0 freeze reserve d deemph amute dac_szc1 dac_szc0
ds723a1 43 cs43l21 freeze controls (freeze) default: 0 function: this function will freeze the previous settings of, and allow modifications to be made to all control port reg- isters without the changes taking effe ct until the freeze is disabled. to have multiple changes in the con- trol port registers take effect simultaneously, en able the freeze bit, make all register changes, then disable the freeze bit. dac de-emphasis control (deemph) default: 0 0 - no de-emphasis 1 - de-emphasis enabled function: note: the data_sel[1:0] bits in reg09h must be set to ?01?b to enable function control. enables the digital filter to apply the standard 15 s/50 s digital de-emphasis filter response for a sample rate of 44.1 khz. analog output auto mute (amute) default: 0 0 - auto mute disabled 1 - auto mute enabled function: enables (or disables) automatic mute of the analog outputs after 8192 ?0? samples on each digital input channel. dac soft ramp and zero cross control (dac_szc[1:0]) default = 10 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: note: the data_sel[1:0] bits in reg09h must be set to ?01?b to enable function control immediate change when immediate change is selected all volume-level changes will take effect immediately in one step. zero cross this setting dictates that signal-level changes, either by gain changes, attenu ation changes or muting, will occur on a signal zero cro ssing to minimize audible artifacts. t he requested level change will occur after a timeout period between 1024 and 2048 sample periods (2 1.3 ms to 42.7 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and imple- mented for each channel. note: the lim_srdis bit is ignored.
44 ds723a1 cs43l21 soft ramp soft ramp allows level changes, either by gain change s, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 db steps, from the cu rrent level to the new level at a rate of 0.5 db per 4 left/right clock periods. soft ramp on zero crossing this setting dictates that signal-level changes, eith er by gain changes, attenuation changes or muting, will occur in 1/8 db steps and be impl emented on a signal zero crossing . the 1/8 db level change will occur after a timeout period between 512 and 1024 sample perio ds (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the ze ro cross function is independently monitored and im- plemented for each channel. note: the lim_srdis bit is ignored. 6.7 pcmx mixer volume control: pcma (address 10h) & pcmb (address 11h) note: the data_sel[1:0] bits in reg09h must be set to ?0 1?b to enable function control in this register. pcmx mixer channel mute (mute_pcmmixx) default = 1 0 - disabled 1 - enabled function: the pcm channel x input to the outp ut mixer will mute when enabled. the muting function is affected by the dacx soft and zero cr oss bits (dacx_szc[1:0]). pcmx mixer volume control (pcmmixx_vol[6:0]) default: 000 0000 function: the level of the pcmx input to the output mixer can be adjusted in 0.5 db increments as dictated by the dacx soft and zero cross bits (dacx_szc[1:0]) from +12 to -51.5 db. levels are decoded as described in the table above. 7 6543210 mute_ pcmmixx pcmmixx_ vol6 pcmmixx_ vol5 pcmmixx_ vol4 pcmmixx_ vol3 pcmmixx_ vol2 pcmmixx_ vol1 pcmmixx_ vol0 binary code volume setting 001 1000 +12.0 db 000 0000 0 db 111 1111 -0.5 db 111 1110 -1.0 db 001 1001 -51.5 db
ds723a1 45 cs43l21 6.8 beep frequency & timing configuration (address 12h) note: the data_sel[1:0] bits in reg09h must be set to ?01?b to enable function control in this register. beep frequency (freq[3:0]) default: 0000 function: the frequency of the beep signal can be adjusted from 260.87 hz to 21 81.82 hz. beep frequency will scale directly with sample rate, fs, but is fixed at the nominal fs within each speed mode. refer to figure 10 on page 26 for single, multiple and co ntinuous beep config urations using the repeat and beep bits. beep on time duration (ontime[3:0]) default: 0000 function: the on-duration of t he beep signal can be adjuste d from approximately 86 ms to 5.2 s. the on-duration will scale inversely with sample rate, fs, but is fixed at the nominal fs within each speed mode. refer to figure 10 on page 26 for single-, multiple- and co ntinuous-beep config urations using the repeat and beep bits. 76543210 freq3 freq2 freq1 freq0 onti me3 ontime2 ontime1 ontime0 freq[3:0] frequency fs = 12, 24, 48 or 96 khz pitch 0000 260.87 hz c4 0001 521.74 hz c5 0010 585.37 hz d5 0011 666.67 hz e5 0100 705.88 hz f5 0101 774.19 hz g5 0110 888.89 hz a5 0111 1000.00 hz b5 1000 1043.48 hz c6 1001 1200.00 hz d6 1010 1333.33 hz e6 1011 1411.76 hz f6 1100 1600.00 hz g6 1101 1714.29 hz a6 1110 2000.00 hz b6 1111 2181.82 hz c7 time[3:0] on time fs = 12, 24, 48 or 96 khz 0000 86 ms 1111 5.2 s
46 ds723a1 cs43l21 6.9 beep off time & volume (address 13h) note: the data_sel[1:0] bits in reg09h must be set to ?0 1?b to enable function control in this register. beep off time (offtime[2:0]) default: 000 function: the off-duration of the beep signal can be adjusted from approximately 75 ms to 680 ms. the off-duration will scale inversely with sample rate, fs, but is fixe d at the nominal fs within each speed mode. refer to figure 10 on page 26 for single-, multiple- and continuous- beep configurations using the repeat and beep bits. beep volume (bpvol[4:0]) default: 00000 function: the level of the beep into the output mixer can be adjusted in 2.0 db increments from +12 db to -50 db. refer to figure 10 on page 26 for single-, multiple- and continuous -beep configurations using the repeat and beep bits. levels are decoded as described in the table above. 76543210 offtime2 offtime1 offtime0 bpvol4 bpvol3 bpvol2 bpvol1 bpvol0 offtime[2:0] off time fs = 12, 24, 48 or 96 khz 000 1.23 s 001 2.58 s 010 3.90 s 011 5.20 s 100 6.60 s 101 8.05 s 110 9.35 s 111 10.80 s binary code volume setting 00110 +12.0 db 00000 0 db 11111 -2 db 11110 -4 db 00111 -50 db
ds723a1 47 cs43l21 6.10 beep configuration & tone configuration (address 14h) note: the data_sel[1:0] bits in reg09h must be set to ?01?b to enable function control in this register. repeat beep (repeat) default: 0 0 - disabled 1 - enabled function: this bit is used in conjunction with the beep bit to mi x a continuous or periodic beep with the analog output. refer to figure 10 on page 26 for a description of each configuration option. beep (beep) default: 0 0 - disabled 1 - enabled function: this bit is used in conjunction with the repeat bit to mix a continuous or peri odic beep with the analog output. note: re-engaging the beep before it has complete d its initial cycle will cause the beep signal to remain on for the maximum ontime duration. refer to figure 10 on page 26 for a description of each con- figuration option. treble corner frequency (treb_cf[1:0]) default: 00 00 - 5 khz 01 - 7 khz 10 - 10 khz 11 - 15 khz function: the treble corner frequency is user selectable as shown above. bass corner frequency (bass_cf[1:0]) default: 00 00 - 50 hz 01 - 100 hz 10 - 200 hz 11 - 250 hz function: the bass corner frequency is us er-selectable as shown above. 76543210 repeat beep reserved treb_cf1 treb_cf0 bass_cf1 bass_cf0 tc_en
48 ds723a1 cs43l21 tone control enable (tc_en) default = 0 0 - disabled 1 - enabled function: the bass and treble tone control features are active when this bit is enabled. 6.11 tone control (address 15h) note: the data_sel[1:0] bits in reg09h must be set to ?0 1?b to enable function control in this register. treble gain level (treb[3:0]) default: 1000 db (no treble gain) function: the level of the shelving treble gain filter is set by treble gain level. the leve l can be adjusted in 1.5 db increments from +12.0 to -10.5 db. bass gain level (bass[3:0]) default: 1000 db (no bass gain) function: the level of the shelving bass gain filter is set by bass gain level. the level can be adjusted in 1.5 db in- crements from +10.5 to -10.5 db. 76543210 treb3 treb2 treb1 treb0 bass3 bass2 bass1 bass0 binary code gain setting 0000 +12.0 db 0111 +1.5 db 1000 0 db 1001 -1.5 db 1111 -10.5 db binary code gain setting 0000 +12.0 db 0111 +1.5 db 1000 0 db 1001 -1.5 db 1111 -10.5 db
ds723a1 49 cs43l21 6.12 aoutx volume control: aouta (address 16h) & aoutb (address 17h) note: the data_sel[1:0] bits in reg09h must be set to ?01?b to enable function control in this register. aoutx volume control (aoutx_vol[7:0]) default = 00h function: the analog output levels can be adjusted in 0.5 db incr ements from +12 to -102 db as dictated by the dac soft and zero cross bits (dacx_szc[1:0]). levels are decoded in unsigned binary as described in the table above. note: when the limiter is enabled, the aout volume is automatically contro lled and should not be ad- justed manually. alternative volu me control may be achieved us ing the pcmmixx_vol[6:0] bits. 6.13 pcm channel mixer (address 18h) note: the data_sel[1:0] bits in reg09h must be set to ?01?b to enable function control in this register. channel mixer (pcmx[1:0]) default: 00 function: implements mono mixes of the left and right ch annels as well as a left/right channel swap. 76543210 aoutx_vol7 aoutx_vol6 aoutx_vo l5 aoutx_vol4 aoutx_vol3 aout x_vol2 aoutx_vo l1 aoutx_vol0 binary code volume setting 0001 1000 +12.0 db 0000 0000 0 db 1111 1111 -0.5 db 1111 1110 -1.0 db 0011 0100 -102 db 0001 1001 -102 db 76543210 pcma1 pcma0 pcmb1 pcmb0 reserved reserved reserved reserved pcma[1:0] aouta pcmb[1:0] aoutb 00 l 00 r 01 01 10 10 11 r 11 l lr + 2 ------------ lr + 2 ------------
50 ds723a1 cs43l21 6.14 limiter threshold szc disable (address 19h) note: the data_sel[1:0] bits in reg09h must be set to ?0 1?b to enable function control in this register. maximum threshold (max[2:0]) default: 000 function: sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack rate. bass, treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an attack. cushion threshold (cush[2:0]) default: 000 function: sets a cushion level below full scale . this setting is usually set slig htly below the maximum (max[2:0]) threshold. the limiter uses this cush ion as a hysteresis point for the in put signal as it maintains the signal below the maximum as well as below the cushion settin g. this provides a more natural sound as the limiter attacks and releases. 76543210 max2 max1 max0 cush2 cush1 cush0 lim_srdis lim_zcdis max[2:0] threshold setting (db) 000 0 001 -3 010 -6 011 -9 101 -12 101 -18 110 -24 111 -30 cush[2:0] threshold setting (db) 000 0 001 -3 010 -6 011 -9 101 -12 101 -18 110 -24 111 -30
ds723a1 51 cs43l21 limiter soft ramp disable (lim_srdis) default: 0 0 - off 1 - on function: overrides the dac_szc setting. when this bit is set, the limiter attack and release rate will not be dictated by the soft ramp setting. note: this bit is ignored wh en the zero-cross function is enabled (i.e. when dac_szc[1:0] = ?01?b or ?11?b.) limiter zero cross disable (lim_zcdis) default: 0 0 - off 1 - on function: overrides the dac_szc setting. when this bit is set, the limiter attack and release rate will not be dictated by the zero-cross setting. 6.15 limiter release rate register (address 1ah) note: the data_sel[1:0] bits in reg09h must be set to ?01?b to enable function control in this register. peak detect and limiter enable (limit_en) default: 0 0 - disabled 1 - enabled function: limits the maximum signal amplitude to prevent clipping when this functi on is enabled. peak signal limiting is performed by digital attenuation. note: when the limiter is enabled, the aout vo lume is automatically controlled and should not be adjusted manually. alternative volume control may be realized using the pcmmixx_vol[6:0] bits. peak signal limit all channels (limit_all) default: 1 0 - individual channel 1 - both channel a & b function: when set to 0, the peak si gnal limiter will limit the ma ximum signal amplitude to prevent clipping on the spe- cific channel indicating clipping. th e other channels will not be affected. when set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both channels in response to any single channel indicating clipping. 76543210 limit_en limit_all rrate5 rrate4 rrate3 rrate2 rrate1 rrate0
52 ds723a1 cs43l21 limiter release rate (rrate[5:0]) default: 111111 function: sets the rate at which the limiter releases the digita l attenuation from levels below the minimum setting in the limiter threshold register, and returns the analog output level to the aoutx_vol[7:0] setting. the limiter release rate is user se lectable but is also a function of the sampling frequency, fs, and the dac_szc setting unless the disable bit is enabled. 6.16 limiter attack rate register (address 1bh) note: the data_sel[1:0] bits in reg09h must be set to ?0 1?b to enable function control in this register. limiter attack rate (arate[5:0]) default: 000000 function: sets the rate at which the limiter attenuates the anal og output from levels above the maximum setting in the limiter threshold register. the limiter attack rate is user-sel ectable but is also a function of the sampling frequency, fs, and the dac_szc setting unless the disable bit is enabled. 6.17 status (address 20h) (read only) for all bits in this register, a ?1? means the associated error condition has occurred at least once since the register was last read. a ?0? means the associated er ror condition has not occurred since the last reading of the register. reading the register resets all bits to 0. serial port clock error (sp_clk error) default: 0 function: indicates an invalid mclk to lrck ratio. see ?serial port clocking? sectio n on page 28?serial port clock- ing? on page 28 for valid clock ratios. note: on initial power up and applicatio n of clocks, this bit will be high as the serial port re-synchronizes. binary code release time 000000 fastest release 111111 slowest release 76543210 reserved reserved arate5 arate4 arate3 arate2 arate1 arate0 binary code attack time 000000 fastest attack 111111 slowest attack 76543210 reserved sp_clkerr spea_ovfl speb_ovfl pcma _ovfl pcmb_ovfl reserved reserved
ds723a1 53 cs43l21 signal processing engine overflow (spex_ovfl) default: 0 function: indicates a digital overflow condition within the data path after the signal processing engine. pcmx overflow (pcmx_ovfl) default: 0 function: indicates a digital overflow condition within the data path of the pcm mix. 6.18 charge pump frequency (address 21h) charge pump frequency (chrg_freq[3:0]) default: 0101 function: alters the clocking frequency of the charge pump in 1/(n+2) fractions of the dac oversampling rate, 128fs, should the switching frequen cy interfere with other system frequencies such as th ose in the am radio band. note: distortion performance may be affected. 76543210 chrg_freq 3 chrg_freq 2 chrg_freq 1 chrg_freq 0 reserved reserved reserved reserved n chrg_freq[3:0] frequency 0 0000 ... ... 15 1111 64xfs n2 + ---------------- -
54 ds723a1 cs43l21 7. analog performance plots 7.1 headphone thd+n versus output power plots test conditions (unless otherwise sp ecified): input test signal is a 997 hz sine wave; measurement band- width is 10 hz to 20 khz; fs = 48 khz. plots were ta ken from the cdb43l21 using an audio precision an- alyzer. g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -10 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 d b r a 0 80m 10m 20m 30m 40m 50m 60m 70m w figure 21. thd+n vs. output power per channel at 1.8 v (16 ? load) va_hp = va = 1.8 v note: graph shows the out- put power per channel (i.e. output power = 23 mw into single 16 ? and 46 mw into stereo 16 ? with thd+n = - 75 db). g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -10 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 d b r a 0 80m 10m 20m 30m 40m 50m 60m 70m w figure 22. thd+n vs. output power per channel at 2.5 v (16 ? load) va_hp = va = 2.5 v note: graph shows the out- put power per channel (i.e. output power = 44 mw into single 16 ? and 88 mw into stereo 16 ? with thd+n = - 75 db).
ds723a1 55 cs43l21 g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -20 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 d b r a 0 60m 6m 12m 18m 24m 30m 36m 42m 48m 54m w figure 23. thd+n vs. output power per channel at 1.8 v (32 ? load) va_hp = va = 1.8 note: graph shows the out- put power per channel (i.e. output power = 22 mw into single 32 ? and 44 mw into stereo 32 ? with thd+n = - 75 db). g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -20 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 d b r a 0 60m 5m 10m 15m 20m 25m 30m 35m 40m 45m 50m 55m w figure 24. thd+n vs. output power per channel at 2.5 v (32 ? load) va_hp = va = 2.5 v note: graph shows the out- put power per channel (i.e. output power = 42 mw into single 32 ? and 84 mw into stereo 32 ? with thd+n = - 75 db).
56 ds723a1 cs43l21 7.2 headphone amplifier efficiency the architecture of the headphone amplifier is that of typical class ab amplifiers . test conditions (unless otherwise specified): input test signal is a 997 hz si ne wave; power consumption mode 6 - stereo playback w/16 ? load. hp_gain = 1.1430. best efficiency is rea lized when the amplifier outputs maximum power. figure 25. power dissipation vs. output power into stereo 16 ? va_hp = va = 1.8 v figure 26. power dissipation vs. output power into stereo 16 ? (log detail) va_hp = va = 1.8 v
ds723a1 57 cs43l21 8. example system clock frequencies 8.1 auto detect enabled *the?mclkdiv2? pin 4 must be set hi. sample rate lrck (khz) mclk (mhz) 1024x 1536x 2048x* 3072x* 8 8.1920 12.2880 16.3840 24.5760 11.025 11.2896 16.9344 22.5792 33.8688 12 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 512x 768x 1024x* 1536x* 16 8.1920 12.2880 16.3840 24.5760 22.05 11.2896 16.9344 22.5792 33.8688 24 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 256x 384x 512x* 768x* 32 8.1920 12.2880 16.3840 24.5760 44.1 11.2896 16.9344 22.5792 33.8688 48 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 128x 192x 256x* 384x* 64 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640
58 ds723a1 cs43l21 8.2 auto detect disabled sample rate lrck (khz) mclk (mhz) 512x 768x 1024x 1536x 2048x 3072x 8 - 6.1440 8.1920 12.2880 16.3840 24.5760 11.025 - 8.4672 11.2896 16.9344 22.5792 33.8688 12 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 256x 384x 512x 768x 1024x 1536x 16 - 6.1440 8.1920 12.2880 16.3840 24.5760 22.05 - 8.4672 11.2896 16.9344 22.5792 33.8688 24 6.1440 9.2160 12.288 0 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 256x 384x 512x 768x 32 8.1920 12.2880 16.3840 24.5760 44.1 11.2896 16.9344 22.5792 33.8688 48 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 128x 192x 256x 384x 64 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640
ds723a1 59 cs43l21 9. pcb layout considerations 9.1 power supply, grounding as with any high-resolution converter, the cs43l21 re quires careful attention to power supply and ground- ing arrangements if its potentia l performance is to be realized. figure 1 on page 9 shows the recommended power arrangements, with va and va_hp connected to clean supplies. vd, which powers the digital circuit- ry, may be run from the system logic supply. alternativ ely, vd may be powered from the analog supply via a ferrite bead. in this case, no additi onal devices should be powered from vd. extensive use of power and ground planes, ground plan e fill in unused areas and surface mount decoupling capacitors are recommended. decoupling capacitors shoul d be as close to the pins of the cs43l21 as pos- sible. the low value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the cs43l21 to minimize inductance effects. all signals, especially clocks, should be kept away from the filt+ and vq pi ns in order to avoid unwanted coupling into the modulators. the filt+ and vq decoupling capacitors, particularly the 0.1 f, must be positioned to minimize the electrical path from filt+ and agnd. the cs43l21 evaluation board demonstrates the optimum layout and power supply arrangements. 9.2 qfn thermal pad the cs43l21 is available in a compact qfn package. the under side of the qfn package reveals a large metal pad that serves as a thermal relief to provide fo r maximum heat dissipation. this pad must mate with an equally dimensioned copper pad on the pcb and must be electrically connected to ground. a series of vias should be used to connect this copper pad to one or more larger ground planes on other pcb layers. in split ground systems, it is recommended that th is thermal pad be connected to agnd for best perfor- mance. the cs43l21 evaluation board demonstrates the optimum thermal pad and via configuration.
60 ds723a1 cs43l21 10.digital filters figure 27. passband ripple figure 28. stopband figure 29. transition band figure 30. transition band (detail)
ds723a1 61 cs43l21 11.parameter definitions dynamic range the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specified band width made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measure- ment. this measurement technique has been accept ed by the audio engineer ing society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified band width (typically 10 hz to 20 kh z), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right cha nnel pairs. measured for each channel at the convert- er's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channel pairs. units in decibels. gain error the deviation from the nominal full-scale an alog output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv.
62 ds723a1 cs43l21 12.package dimensions 1. dimensioning and tolerance per asme y 14.5m-1995. 2. dimensioning lead width applies to the plated te rminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. thermal characteristics inches millimeters note dim min nom max min nom max a----0.0394----1.00 1 a1 0.0000 -- 0.0020 0.00 -- 0.05 1 b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1 , 2 d 0.1969 bsc 5.00 bsc 1 d2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1 e 0.1969 bsc 5.00 bsc 1 e2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1 e 0.0197 bsc 0.50 bsc 1 l 0.0118 0.0157 0.0197 0.30 0.40 0.50 1 jedec #: mo-220 controlling dimension is millimeters. parameter symbol min typ max units junction to ambient thermal impedance 2 layer board 4 layer board ja - - 52 38 - - c/watt side view a1 bottom view top view a pin #1 corner d e d2 l b e pin #1 corner e2 32l qfn (5 x 5 mm body ) package drawing
ds723a1 63 cs43l21 13.ordering information 14.references 1. cirrus logic, an18: layout and design rules for data converters and other mixed signal devices , version 6.0, february 1998. 2. cirrus logic, how to achieve optimum performance fr om delta-sigma a/d and d/a converters , by steven harris. presented at the 93rd convention of the audio engineering society, october 1992. 3. cirrus logic, a fifth-order delta-sigma modulator with 110 db audio dynamic range , by i. fujimori, k. ha- mashita and e.j. swanson. paper pr esented at the 93rd conv ention of the audio engineering society, oc- tober 1992. 4. philips semiconductor, the i2c-bus specification: version 2.1 , january 2000. http://www.semicondu ctors.philips.com 15.revision history product description package pb-free grade temp range container order # cs43l21 low-power stereo d/a with hp amp for portable apps 32l-qfn yes commercial -10 to +70 c rail cs43l21-cnz tape & reel cs43l21-cnzr automotive -40 to +85 c rail cs43l21-dnz tape & reel CS43L21-DNZR cdb43l21 cs43l21 evaluation board - no - - - cdb43l21 revision changes a1 initial release contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com. important notice "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc . and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information t o verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limit ation of liability. no responsibility is assumed by cirrus fo r the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, co pyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives conse nt for copies to be made of the infor- mation only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this conse nt does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve po tential risks of death, perso nal injury, or severe prop- erty or environmental damage (?critical applications?). cirr us products are not designed, au thorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, automotive safety or security de- vices, life support products or other critical applications. inclusion of cirrus products in such applications is under- stood to be fully at the customer?s ri sk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchan tability and fitness for par ticular purpose, with rega rd to any cirrus product that is used in such a manner. if the customer or customer?s cu stomer uses or permits the use of cirrus products in critical applications, customer agrees, by such u se, to fully indemnify cirrus, its officers , directors, employees, distributors and other agents from any and all liability, including attorneys? fe es and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor. spi is a trademark of motorola, inc.

▲Up To Search▲

Price & Availability of CS43L21-DNZR

	To Download CS43L21-DNZR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .